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 The receiver (Rx) test

Should be noted that the EDID test project issues

In the process of testing often fail in these tests with EDID related projects. If you are familiar with the relevant requirements specification, through is relatively easy.For example, the relevant requirements in the first 128 bytes of the EDID mustprovide "Monitor Range Limit Header" and "Monitor Name Header", but if these twoitems were less than 18 bytes, words, need ended with 0x0A and 0x20 to fill the remaining bytes. Another commonly encountered in the EDID test question is, can not be short video descriptors in EDID (SVD) module and submit the ability toreturn (CDF), in CDF format does not show that support the support in the SVDmodule of EDID, or is the opposite of.

TMDS signal differential impedance matching

When designing a circuit board will consider TMDS signal differential impedance matching requirements, but often fail in the test, because the ESD protection devices or common mode choke coil with the inhibition of EMI parasitic capacitanceis too large, resulting in the test failure. Impedance test chart, may require themanufacturers to provide relevant information.

Capacitor voltage test of DDC/CEC channel

This test is very high project failure rate. The failure reason most becauseMOSFET devices used for capacitance voltage conversion is too large, the use ofsuggestions on the DDC channel MOSFET devices Ciss and Coss should be below 10pF.

HPD output voltage

HDMI protocol when the HDMI +5V input is 0V, the HPD voltage should be more than 0V, and less than 0.4V. Here is the most simple method is to direct routingresistance HDMI input +5V voltage port in series with a 1K back to the HPD pins.Recommend the use of a simple transistor switch circuit to control the HPD pin,which can take the initiative to inform the downstream equipment in source enddevice is ready or tell the source end device to start some verify the action, such as HDCP, it can enhance the compatibility of the equipment.

Video format support

In this test, the test device that supports 50Hz for 50Hz ± 0.5% for all HDMI inputport can support video format (49.75Hz and 50.25Hz), and support for 59.94Hz or 60Hz devices to 59.94－0.5% (59.64Hz) and 60+0.5% (60.3Hz) field changesupport. In the software design need to pay attention to the video format tolerancerequirements.

Source end testing (Tx)

Test EDID

For the HDMI source end equipment requirements must support the "EnhancedDDC" protocol, can use the pointer 0x60 information after the first 256 bytes read isto read the EDID information receiving terminal equipment. Although the vast majority of customers using EDID 256 bytes of information, but the HDMI test willdetect read 4 blocks (each 128 bytes), which is 512 bytes of information capacity.The existence of multiple pieces of information from the EDID content of the 0x7Eaddress that. Often only test the ability to support the first 256 bytes of the test,while ignoring the segment request.

+5V power output

No series resistance in power output HDMI output port. Specifications in HDMI Tx test will be connected to a 55mA load current drain, and then test the output voltage, the voltage between the 4.8V and 5.3V requirements. If the series with a 10 ohm resistor, the output voltage, 5 10x0.055 = 4.45V < 4.8V, this test fails.

DDC/CEC measurement.

In the consumer electronic products processing HDMI port control (CEC) pin, HDMI port thirteenth pins, if the product does not support the CEC function, this pin can be suspended. But some products often doesn't support the CEC function,common pin and the pin is connected to the main processing chip, has the futureexpansion of the use of, the need to pay attention to this pin some limitations in theelectrical properties and physical connections, such as the capacitor shall be less than 100pF, otherwise it will lead to not by HDMI test.